This application is related by subject matter to a commonly assigned application entitled xe2x80x9cProgrammable Semiconductor Memoryxe2x80x9d filed concurrently herewith.
1. Field of the Invention
This invention relates to a programmable semiconductor memory using non-volatile transistors as memory cells from which data can be electrically erased. It particularly relates to a non-volatile semiconductor memory in which data stored in a plurality of memory cells may be erased simultaneously, in units of a block, or in units of a column. Data may be written to the memory a cell (or bit) at a time.
2. Description of the Prior Art
A non-volatile transistor memory which permits erasure of data is known as an EPROM (Erasable and Programmable Read Only Memory). An EPROM from which data may be erased electrically is called an E2 PROM (Electrically Erasable PROM). E2 PROMs have been developed which permit the simultaneous erasure of data stored in a plurality of memory cells. Such an E2 PROM is disclosed in xe2x80x9cA 128K Flash EEPROM Using Double Polysillcon Technologyxe2x80x9d, pp. 76-77 of xe2x80x9c1987 IEEE International Solid State Circuits Conference, Digest of Technical Papers.xe2x80x9d
FIG. 11 is a circuit diagram depicting a conventional E2 PROM memory cell array using the cells described in the above-mentioned document. In this Figure, memory cells 90 consist of non-volatile transistors having a floating gate electrode and a control gate electrode. Data erasure may be effected electrically. Memory cells 90 are arranged in a row and column matrix. The drains of each memory cell 90 in a given row of memory cells (which are horizontal as seen In the drawing) are respectively coupled to the same one of bit lines 91. The sources of the memory cells 90 in a given row of memory cells are respectively coupled to the same one of ground lines 92. The control gate electrodes of the memory cells 90 in a given column of memory cells (which are vertical as seen in the drawing) are respectively coupled to the same one of column lines 93. In this memory, data may be read or written by the selective imposition of set voltages on a given bit line 91 and column line 93 to select a particular 1-bit cell. Block data erasure of all the bits can be effected by the simultaneous imposition of a set voltage on all the bit lines 91.
This memory permits large-scale integration of cells since each cell or bit consists of a single non-volatile transistor. However, data erasure may only be effected in the cells simultaneously or in units of a row. It is not possible to effect data erasure in units of a byte, the processing unit for parallel read/write memories.
The prior art does disclose an E2 PROM which permits data erasure in byte units. Reference is made, for example to xe2x80x9cA Million-cycle CMOS 256K EEPROMxe2x80x9d, pp. 78-79 of xe2x80x9c1987 IEEE International Solid-State Circuits Conference, Digest of Technical Papers.xe2x80x9d However, large-scale integration of cells is not possible with the memory disclosed therein, since each 1-bit memory cell comprises two or four transistors.
It is therefore an object of the present invention to provide a device to control the operations of a programmable semiconductor memory wherein the reading, writing and electrical erasure of data is effected in 8 bit (1 byte) units.
Another object of this invention is to provide a programmable semiconductor memory wherein a high integration density can be achieved by reducing the number of wires and the number of contacts.
Another object of this invention is to provide a programmable semiconductor memory wherein the reading, writing, and electrical erasure of data in 8 bit (1 byte) units can be achieved.
Yet another object of this invention is to provide a programmable semiconductor memory with high integration density wherein the electrical data erasure is made in byte units.
A further object of this invention is to provide a programmable semiconductor memory whose manufacturing cost is low.
The non-volatile semiconductor memory of this invention comprises a series circuit unit having at least two memory cells connected in series. Each memory cell consists of a non-volatile transistor having a floating gate electrode, a control gate electrode, and an erase gate electrode. Data stored in the memory cells may be erased electrically.
One end of each of the series circuit units in a given column is coupled to a common bit line. The erase gate electrodes of the memory cells in a given series circuit unit are commonly connected. The control gate electrodes of the memory cells in a given row of memory cells are coupled to a common row line. An erase line is provided on which an erase voltage is imposed at times of data erasure. Also included is means for imposing a set voltage on the bit lines and row lines to sequentially read or write data in the memory cells comprising a series circuit unit.
The present invention also concerns an address selector for use with a programmable memory having a plurality of memory cells. The address selector has means for sequentially selecting the memory cells in a predetermined fashion. The data is transferred along data lines coupled to the memory cells and a plurality of temporary storage cells. The temporary storage cells are controlled by address data to select one of the temporary storage cells for reading data from the memory cells and writing data into the memory cells.